Legal
Public facts only.
This website is a public product overview. It is not a JEDEC extract, not a foundry PDK, not a datasheet guarantee, and not an intellectual property license.
Numbers that are not in a cited public source or a founder-locked SKU are left empty. Vendor marketing pin-rates are labeled as such and are not FairView locks. Invention-disclosure pillars A–E are internal claim directions for counsel. They are proprietary trade secrets.
Export control: an HBM4 controller plus a MPU attach is likely ECCN-sensitive. This site is not a classification, a license, or advice on how to ship restricted items. Design-in and any eventual silicon follow the export-control laws that apply to the customer, the node, and the destination. We will not market around those rules.
Must not claim
- Invent unpublished JEDEC timings (tRFC, tREFI, tRCD, tRP, tRAS, tFAW, tCCD).
- Select a FairView VDDQ or VDDC. The legal sets are vendor-specific options.
- Lock Samsung 11.7 Gbps, SK hynix 10 GT/s, or SPHBM4 46 GT/s as FairView numbers.
- Claim FairView owns the 1T1C DRAM array or a secret cell process.
- Treat UCIe, CXL.mem, or optical I/O as on-package HBM bandwidth.
- Write 128 GB/s PCIe as if it were Gallium TB/s.
- Claim unfiled IP. Five pillars are internal invention-disclosure directions only.
- Quote 2 TB/s from a 2048-bit teaching lock, or confuse 8×1024 with 8×2048 (16,384-bit HBM4).