Specifications
Public datasheet. Empty knobs stay empty.
Pin-rate lock is 8.0 Gbps, the JESD270-4 public baseline. 6.4 and 9.6 exist only as compiler options, not as FairView production promises. Vendor 10 / 11.7 / 13 Gbps rows are omitted on purpose.
Bandwidth workbook
B = W × R / 8000 TB/s. Six- and eight-cube columns are legal later re-locks, not first silicon.| W_DQ | R | tCK (ns) | B stack | N = 4 | N = 6 | N = 8 | Note |
|---|
| 2048 | 8 | 0.250 | 2.048 | 8.192 | 12.288 | 16.384 | Gallium-H4 lock |
| 512 | 32 | n/a | 2.048 | 8.192 | 12.288 | 16.384 | Gallium-S4 identity (4×8) |
Capacity workbook
C_GB = N_hi × D_Gb / 8. First product BOM is 12-hi × 24 Gb = 36 GB/cube. Teaching max 16-hi is not bring-up.| Height | 24 Gb die (GB) | 32 Gb die (GB) |
|---|
| 4-hi | 12 | 16 |
| 8-hi | 24 | 32 |
| 12-hi | 36 | 48 |
| 16-hi | 48 | 64 |
Gallium SKUs
| SKU | Attach | DQ | B stack | First package | Status |
|---|
| FV-GL-H4 | JESD270-4 silicon interposer | 2048 | 2.048 TB/s | 4 × 36 GB | First tape-out |
| FV-GL-S4 | JESD330-4 organic substrate | 512 | 2.048 TB/s | 4 × 36 GB | Scale-down SKU |
| FV-GL-HX | Dual-mode · one credit / QoS plane | 2048 | 2.048 TB/s | 4 × 36 GB | Controller chiplet |
Stallion SKUs
| SKU | SM | Clock | FP32 | Tensor | HBM (mirrored) | TDP |
|---|
| FV-ST-S100 | 128 | 1.80 GHz | 59.0 TFLOPS | 471.9 TFLOPS | 8.192 TB/s | 800 W |
| FV-ST-S80I | 96 | 1.60 GHz | 19.7 TFLOPS | 629.1 TFLOPS | 8.192 TB/s | 600 W |
Legal voltage option sets
JESD270-4 public option sets. Not a FairView-selected rail. SPHBM4 0.75 V I/O is press-only and is not packed.| Rail | Legal set |
|---|
| VDDQ | 0.7 V · 0.75 V · 0.8 V · 0.9 V |
| VDDC | 1 V · 1.05 V |
| Selected | null until a partner pack cites one |
Standards cited, not extracted
JESD270-4 (April 2025; 270-4A Dec 2025), JESD330-4 document handle, UCIe, CXL 3.1, PCIe 6.0. This page is not a JEDEC extract and not a foundry PDK.