Specifications

Public datasheet. Empty knobs stay empty.

Pin-rate lock is 8.0 Gbps, the JESD270-4 public baseline. 6.4 and 9.6 exist only as compiler options, not as FairView production promises. Vendor 10 / 11.7 / 13 Gbps rows are omitted on purpose.

Bandwidth workbook

B = W × R / 8000 TB/s. Flagship package delivers 16.0 TB/s sustained across eight 16-Hi HBM4 stacks (16,384-bit bus).
W_DQ	R	tCK (ns)	B stack	N = 4	N = 6	N = 8	Note
2048	8	0.250	2.048	8.192	12.288	16	Gallium-H4 Flagship (8-Stack, 16,384-bit)
512	32	n/a	2.048	8.192	12.288	16	Gallium-S4 identity (4×8)

Capacity workbook

C_GB = N_hi × D_Gb / 8. Flagship production BOM is 16-Hi × 32 Gb = 64 GB/cube (512 GB across 8 stacks).
Height	24 Gb die (GB)	32 Gb die (GB)
4-hi	12	16
8-hi	24	32
12-hi	36	48
16-hi	48	64

Gallium SKUs

SKU	Attach	DQ	B stack	First package	Status
FV-GL-H4	JESD270-4 silicon interposer	2048	2.048 TB/s	8 × 64 GB (512 GB)	First tape-out
FV-GL-S4	JESD330-4 organic substrate	512	2.048 TB/s	8 × 64 GB (512 GB)	Scale-down SKU
FV-GL-HX	Dual-mode · one credit / QoS plane	2048	2.048 TB/s	8 × 64 GB (512 GB)	Controller chiplet

Stallion SKUs

SKU	SM	Clock	FP32	Tensor	HBM (mirrored)	TDP
FV-ST-S100	128	1.80 GHz	0.15 PFLOPS	4.72 Dense PFLOPS (FP8 / FP4)	16 TB/s	350 W
FV-ST-S80I	96	1.60 GHz	0.02 PFLOPS	629.1 Dense PFLOPS (FP8 / FP4)	16 TB/s	600 W

Legal voltage option sets

JESD270-4 public option sets. Not a FairView-selected rail. SPHBM4 0.75 V I/O is press-only and is not packed.
Rail	Legal set
VDDQ	0.7 V · 0.75 V · 0.8 V · 0.9 V
VDDC	1 V · 1.05 V
Selected	null until a partner pack cites one

Standards cited, not extracted

JESD270-4 (April 2025; 270-4A Dec 2025), JESD330-4 document handle, UCIe, CXL 3.2, PCIe 6.0. This page is not a JEDEC extract and not a foundry PDK.

Public specifications