Gallium · FV-GL-HX

Gallium HX

Separate chiplet. 330-4 wrapper is a stub on first tape-out.

Controller chiplet

Editorial render of a partner HBM cube stack. Not a pinout.

Editorial 16-high partner cube. FairView does not claim the 1T1C array.

Public product lock. Empty JEDEC timings are omitted on purpose.
ParameterValue
SKUFV-GL-HX
AttachDual-mode · one credit / QoS plane
Attach modedual
External DQ2048 bits
Pin / identity rateMode selects width. First die straps H4.
Bandwidth / stack2.048 TB/s
First package cubes8
First package bandwidth16 TB/s
Stack height16-hi
Die density32 Gb
Capacity / cube64 GB (= 16 × 32 / 8)
Capacity / package512 GB
Channels / pseudo-channels32 / 64
tCKFollows strapped 270-4 pin rate
tRFC / tREFInot in pack — do not invent
VDDQ / VDDClegal option sets only; no selected rail

What this SKU is not

Not a Samsung 11.7 Gbps bin. Not 3.3 TB/s. Not a FairView DRAM factory. SPHBM4 46 GT/s is press-only and is not listed as a FairView lock.

All Gallium SKUsDesign-in
FV-GL-HX Gallium HX