Gallium Series

HBM4 as a chipset, not a slide.

Host controller, dual-mode attach, RAS policy, and package roles — JEDEC-compatible, MPU-aware.

FairView is not a DRAM IDM on day one. Cubes are partnered known-good stacks. Differentiation is the controller, the attach, and the Stallion contract.

Brand study — liquid-metal metaphor for Gallium. Not a pinout and not a physical stack photograph.

First SKU
FV-GL-H4JESD270-4 · 2048-bit · 8.0 Gbps
Channels
32 / 64Independent channels / pseudo-channels
First package
16 TB/s512 GB · 8 × 64 GB (16-Hi)
Controller
FV-GL-HXSeparate chiplet · dual-mode API frozen

SKU matrix

H4 first. S4 later. HX is the plane.

FV-GL-H4

Gallium H4

First tape-out

Flagship HBM4 attach. 8-stack 16-Hi configuration delivering 512 GB unified memory across 16,384-bit bus. Hardware-managed 128k-entry KV-cache (fv_kv_cache) with Processing-in-Memory (PIM) expert-weight staging.

  • Attachjesd270_4
  • External DQ2048-bit
  • Stack bandwidth2.048 TB/s
FV-GL-S4

Gallium S4

Scale-down SKU

Same partner cubes, organic package. Not first silicon.

  • Attachjesd330_4
  • External DQ512-bit
  • Stack bandwidth2.048 TB/s
FV-GL-HX

Gallium HX

Controller chiplet

Separate chiplet. 330-4 wrapper is a stub on first tape-out.

  • Attachdual
  • External DQ2048-bit
  • Stack bandwidth2.048 TB/s

Dual-mode

One credit plane. Two PHY wrappers.

Dual-mode attach with one credit planeStallionGALLIUM-HXone credit / QoS32 logical channelsMode 270-4 · 2048-bit interposer PHY8.0 Gbps · 2.048 TB/s/stackMode 330-4 · 512-bit organic PHY4:1 · identity 32 GT/s ↔ 2.048 TB/sATTACH MUX · FIRST TAPE-OUT STRAPS H4
Dual-mode changes PHY-IF width and serialization only. The credit plane, remap, RAS, and hint ports stay the same.
JESD270-4 channel and pseudo-channel mapONE PARTNER CUBE · 32 × 64 b = 2048 b · 64 PSEUDO-CHANNELSHBM4 cubeCH0 64bCH1 64bCH2–CH30CH31 64bPC0PC1PC0PC1PC0PC1Virtualization sits abovevirt_ch → {cube, phys_ch}Stack always sees CH0–CH31JEDEC map is not a FairView claim
Per-channel independence is a JEDEC property. Cross-channel stalls are legal only for cube-level refresh, thermal, and RAS.
Gallium Series HBM4