Gallium Series
HBM4 as a chipset, not a slide.
Host controller, dual-mode attach, RAS policy, and package roles — JEDEC-compatible, GPU-aware.
FairView is not a DRAM IDM on day one. Cubes are partnered known-good stacks. Differentiation is the controller, the attach, and the Stallion contract.
Brand study — liquid-metal metaphor for Gallium. Not a pinout and not a physical stack photograph.
- First SKU
- FV-GL-H4JESD270-4 · 2048-bit · 8.0 Gbps
- Channels
- 32 / 64Independent channels / pseudo-channels
- First package
- 8.192 TB/s144 GB · 4 × 36 GB
- Controller
- FV-GL-HXSeparate chiplet · dual-mode API frozen
SKU matrix
H4 first. S4 later. HX is the plane.
FV-GL-H4
Gallium H4
First tape-out
Flagship HBM4 attach. First silicon populates this PHY only.
- Attachjesd270_4
- External DQ2048-bit
- Stack bandwidth2.048 TB/s
Gallium S4
Scale-down SKU
Same partner cubes, organic package. Not first silicon.
- Attachjesd330_4
- External DQ512-bit
- Stack bandwidth2.048 TB/s
Gallium HX
Controller chiplet
Separate chiplet. 330-4 wrapper is a stub on first tape-out.
- Attachdual
- External DQ2048-bit
- Stack bandwidth2.048 TB/s
Dual-mode