FairViewSemiconductorDesign-in

Architecture

Four cubes, three dies, two attaches, one QoS plane.

First Stallion package is four partner cubes on a CoWoS-class silicon interposer. Gallium-HX is its own chiplet. Six- and eight-cube SKUs are later memory-slot re-locks, not a second GPU bandwidth.

Flagship package block diagramHost CPU connects over PCIe Gen6 and CXL 3.1 to the I/O die. UCIe carries MMIO to Stallion. Stallion L2 drives Gallium-HX. Gallium drives four partner HBM4 cubes. A sidecar carries command, credit, and telemetry only.PACKAGE · CoWoS-CLASS 2.5D · FIRST SILICON H4-ONLYHost CPUboard / CXL hostI/O DIEPCIe Gen6 x16CXL 3.1UCIe-E → StallionSTALLION COMPUTECommand processor2D mesh NoCSM arrayPartitioned L2Refresh hint engineSidecar APB / UCIeGALLIUM-HX CHIPLETCredit / QoS plane32-ch remapRAS / DRFM policyH4 PHY wrappercube 0cube 1cube 2cube 3HBM datasidecar
Flagship attach. Gallium-HX is a separate chiplet. Cubes are partner DRAM stacks. UCIe never carries HBM beats.
Host / I/OStallionGallium + cubes
Three physically distinct attachesHost CPUI/O dieStallionGallium-HXHBM cubesPCIe / CXLUCIe MMIOHBM data270-4 / 330-4sidecar · credit / hint / therm / RAS
Mixing these identities is the modern “PHY inside the ARM core” mistake. Aggregate TB/s is owned only by Gallium.
Three physically distinct attaches. Mixing their identities is forbidden.
PathProtocolPayloadIdentity owner
Host ↔ I/O diePCIe 6.0 x16 / CXL 3.1Commands, page traffic, poolingI/O die
I/O ↔ StallionUCIe-EMMIO, interrupts, sidecarI/O die
Stallion ↔ Gallium sidecarUCIe-E or on-die APBCredit, refresh hints, thermal, RASSidecar
Stallion L2 ↔ cubesJESD270-4 or JESD330-4All HBM dataGallium memory lock
Dual-mode attach with one credit planeStallionGALLIUM-HXone credit / QoS32 logical channelsMode 270-4 · 2048-bit interposer PHY8.0 Gbps · 2.048 TB/s/stackMode 330-4 · 512-bit organic PHY4:1 · identity 32 GT/s ↔ 2.048 TB/sATTACH MUX · FIRST TAPE-OUT STRAPS H4
Dual-mode changes PHY-IF width and serialization only. The credit plane, remap, RAS, and hint ports stay the same.
JESD270-4 channel and pseudo-channel mapONE PARTNER CUBE · 32 × 64 b = 2048 b · 64 PSEUDO-CHANNELSHBM4 cubeCH0 64bCH1 64bCH2–CH30CH31 64bPC0PC1PC0PC1PC0PC1Virtualization sits abovevirt_ch → {cube, phys_ch}Stack always sees CH0–CH31JEDEC map is not a FairView claim
Per-channel independence is a JEDEC property. Cross-channel stalls are legal only for cube-level refresh, thermal, and RAS.
Gallium-HX logical blocksGALLIUM-HX · CREDIT SHELL · NO ANALOG PHYStallion L2 / NoCHint portThermal sensorsIngress / PC buffersRefresh arbiterRAS policyPer-channel schedulerShared credit QoSVirtual CH remapAttach mode mux270-4 2048b PHY-IF330-4 512b PHY-IF
Dual-mode mux changes pin muxing, not credit counters. Bank-conflict timing stays packed or empty — never invented.
Fused thermal class across cube, controller, and GPUCube sensorController sensorStallion SM sensorThermal fuseCLASS 0–3cool → hotRefresh weightQoS demoteStallion clock req
Class 3 requests a Stallion clock re-lock. It is not a silent Vdd change and not a numeric Tj max.

Encoding-naive PCIe is not HBM

PCIe Gen6 x16 is 16 × 64 / 8 = 128 GB/s raw, and lower after FLIT. It must never appear in the same sentence as Gallium TB/s without an explicit “different attach” clause.