FairViewSemiconductorDesign-in

FairView Semiconductor

The memory lock. The GPU lock. One package.

Gallium is the HBM4 chipset. Stallion is the GPU. Bandwidth is compiled, never sampled. UCIe carries command and telemetry. It is not HBM.

Gallium HBM4Stallion GPUPackage architecture
Per stack · JESD270-4
2.048 TB/s2048 × 8 / 8000
First package
8.192 TB/s4 cubes · 144 GB · 12-hi × 24 Gb
DDR clock
0.250 nstCK = 2 / 8 Gbps · not 250 ns
Stallion S100 FP32
59.0 TFLOPS128 SM × 128 ALU × 2 × 1.8 / 1000

Product families

Two series. One binder rule.

Aggregate HBM bandwidth is owned only by Gallium. Stallion may mirror it for the roofline. Equal TB/s is not equal geometry.

Memory chipset

Gallium Series

Host controller, dual-mode attach, RAS policy, and package roles — JEDEC-compatible, GPU-aware.

GPU / accelerator

Stallion Series

On-package AI GPU. HBM bandwidth is mirrored from Gallium — Stallion does not invent a second TB/s.

Architecture

A die set, not a slogan.

First silicon is four partner cubes on a CoWoS-class interposer, Gallium-HX as its own chiplet, Stallion as the compute die, host I/O on PCIe 6 / CXL 3.1.

Flagship package block diagramHost CPU connects over PCIe Gen6 and CXL 3.1 to the I/O die. UCIe carries MMIO to Stallion. Stallion L2 drives Gallium-HX. Gallium drives four partner HBM4 cubes. A sidecar carries command, credit, and telemetry only.PACKAGE · CoWoS-CLASS 2.5D · FIRST SILICON H4-ONLYHost CPUboard / CXL hostI/O DIEPCIe Gen6 x16CXL 3.1UCIe-E → StallionSTALLION COMPUTECommand processor2D mesh NoCSM arrayPartitioned L2Refresh hint engineSidecar APB / UCIeGALLIUM-HX CHIPLETCredit / QoS plane32-ch remapRAS / DRFM policyH4 PHY wrappercube 0cube 1cube 2cube 3HBM datasidecar
Flagship attach. Gallium-HX is a separate chiplet. Cubes are partner DRAM stacks. UCIe never carries HBM beats.
Host / I/OStallionGallium + cubes

Full attach map

Why FairView

Differentiation that survives a JEDEC lawyer.

Dual-mode, one QoS plane

JESD270-4 (2048-bit interposer) and JESD330-4 (512-bit organic, 4:1) present the same 32 logical channels and the same credit plane to Stallion. First tape-out is H4-only; the S4 wrapper is a stub.

GPU-scheduled refresh

Stallion issues idle-window credits from wavefront drain, barriers, and L2 miss-queue occupancy. Gallium prefers those windows for refresh and directed refresh. Periodic refresh still fires if credits do not arrive.

Channel virtualization

A firmware remap table isolates MIG tenants or a second Stallion die. The stack always sees legal CH0–CH31. Remap is drain-then-commit — never mid-burst.

UCIe sidecar, not the data path

Command, credit, thermal class, and RAS events ride a closed opcode set. There is no data-beat type. HBM read/write never rides UCIe.

Fused thermal class

Cube, controller, and SM sensors fuse into four discrete classes. Class raises refresh weight, demotes unhinted QoS, and at class 3 requests a Stallion clock re-lock. No invented junction-temperature datasheet.

Honest identities

Every number on this site is a public standard fact, a founder-locked SKU, or arithmetic. Empty knobs — tRFC, selected Vdd, vendor marketing bins — stay empty.

Design-in

Controller IP, attach, and a GPU that will not lie about bandwidth.

FairView is not a DRAM IDM. We ship the chipset and the Stallion contract. Cubes are partnered.

Start a design-inPublic specifications