PULSE™ pre-silicon host runtimev0.8.4-alpha Release ›GRID=4 host

PULSE SDK — Pre-silicon host runtime

Host-side programming interface, ISA word packer, and numeric golden for the Stallion GRID=4 instance. Not a device driver. Not foundry GDS. github.com/fairviewsemiconductor/pulse-sdk. torch.compile backend="pulse" is not in this release.

View on GitHub (fairviewsemiconductor/pulse-sdk) ›Release v0.8.4-alpha Notes ›Read FreeToken commentary ›

pulse-quickstart.sh

# PULSE pre-silicon host runtime
git clone https://github.com/fairviewsemiconductor/pulse-sdk.git
cd pulse-sdk
# Not in this release: torch.compile(..., backend="pulse")
./SDK/pulse/run_all_tests.sh

■ This release

Pre-silicon host runtime — this release

In this release: ISA packers A1/B1 and GRID=4 goldens. Not in this release: pulse-opt MLIR, pulse-moe, cycle-accurate pulse-sim, CXL 3.1 driver, torch.compile backend="pulse". PULSE is not a path from MLIR to GDSII. It is not CUDA. FreeToken does not run on Stallion today.

pack_mma / pack_dma

Host word packing for MMA opcode B1 and DMA opcode A1. GRID=4 numeric goldens.

pulse-opt

Not in this release. Not MLIR-to-GDSII. Not a FreeToken lowering pass.

4.72 PFLOPS

TARGET / NOT MEASURED family target. Bring-up 1H 2027 · Product S10 2H 2027.

Developer Program

Technical discussion

Cycle-accurate pulse-sim is not in this release. Public SDK: host runtime. Diligence for RTL is under NDA.

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